The present invention relates generally to programmable logic devices, and more particularly to methods and apparatus to reconfigure programmable logic devices,
Programmable logic devices (PLDs) are gaining popularity as powerful reconfigurable digital circuits. Compared to general purpose microprocessors, they are much faster because they can be tailored to specific tasks. Compared to application specific integrated circuits, PLDs need much less non-recurring engineering cost to implement a design; they also provide faster turnaround for rapid product prototyping and initial or small-volume production.
One type of PLDs that can be programmed by a user is the field programmable gate arrays (FPGA) as illustrated in FIG. 1. An FPGA is typically made up of numerous cells or logic blocks. Each cell includes rewritable configuration memories to program or reconfigure the cell for different tasks, such as adding and subtracting. Reconfiguration is typically done by loading different configuration data into the rewritable configuration memories in each cell. Reconfiguration is not limited to the cells. Interconnects among the cells are also reconfigurable. In this application, both the logic elements in a cell and the interconnects among the cells that can be reconfigurable are known as configurable elements.
In a conventional FPGA, reconfiguration data are loaded into configuration memories serially through shift register elements, with one shift register element controlling the content of a configuration memory unit. To reconfigure the FPGA chip, the data are shifted in serially, one bit at a time, into the shift register elements, and then loaded into the configuration memory units.
One representation of the reconfiguration data is a reconfiguration page. Each page includes information for an entire chip. A page can include 100K bits, with each bit controlling a configuration memory unit for updating one configurable element in an FPGA. Data transfer for such a page of data can take more than a second, and has to be done every time the FPGA is powered up. For numerous applications, reconfiguration data are transferred eve n during normal system operation so as to reconfigure each cell for different tasks on the fly. Thus, to increase the operation speed of FPGAs, reconfiguration time or the time to transfer reconfigurition data to FPGAs should be minimized.
One approach to reduce the reconfiguration time is to increase the width of the bus carrying the reconfiguration data to the shift register elements. With a wider bus, instead of shifting a bit at a time, byte-sized words are transferred. The reconfiguration time is thus reduced based on the width of the bus. However, data with each unit being one or more byte-sized words still have to be transferred serially into the chip.
Another approach to reduce the reconfiguration time is to pre-store reconfiguration data in the chip. For example, pages of reconfiguration data can be pre-stored in on-chip memory, with an on-chip pointer selecting the appropriate configuration page for the configurable elements during data transfer. A FPGA could then be reprogrammed, or reconfigured, simply by writing a new value to this pointer. However, because of silicon area limitations, such a FPGA can only store a limited number of configuration pages. One existing FPGA using this approach has significantly reduced the reconfiguration time, but only for eight configuration pages stored or chip and with 100K bits per page. Additional configuration pages would have to be stored off chip and loaded onto the chip at the regular slower speed.
It should be apparent from the foregoing that there is still a need for methods and apparatus to reduce the reconfiguration time if there are large amount of reconfiguration data.